NXP® SemiconductorsMSE9S12KT256_1L33V
Mask Set ErrataRev. April 08, 2011



MC9S12KT256, Mask 1L33V


Introduction
This errata sheet applies to the following devices:

MC9S12KT256



MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.



MCU Device Date Codes

Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002.



MCU Device Part Number Prefixes

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.



Errata System Tracking Numbers

MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.



Errata Summary


Errata NumberModule affectedBrief DescriptionWork-
around
MUCts01493 S12_cpu Tagged breakpoints missed if tag attach and interrupt are simultaneous NO
MUCts01534 vreg_3v3 Return from STOP malfunction NO
MUCts01654 mcu_9kt256 Reduced flash program temperature range and increased programming time YES
MUCts01677 SFC0064_22BA_HDR Flash test read issue YES
MUCts01861 S12_bdm Possible manipulation of return address when exiting BDM active mode YES
MUCts02387 eets4k EEPROM Program Failure during Sector-Modify YES
MUCts02415 S12_mebi MEBI: Missing ECLK edge on first external access after mode switching YES
MUCts03403 spi SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmission YES
MUCts03468 atd_10b8c ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not work YES
MUCts03543 fts256k2ecc FTS256K2ECC: Blind Spot in Data Compress Command Algorithm YES
MUCts03569 mscan MSCAN: Corrupt ID may be sent in early-SOF condition YES
MUCts03685 atd_10b8c ADC: conversion does not start with 2 consecutive writes to ATDCTL5 YES
MUCts04073 pwm_8b8c PWM: Emergency shutdown input can be overruled YES
MUCts04159 tim_16b8c TIM:Normal Output Compare event happens on setting OC7M bit if OM/OL=0 YES
MUCts04161 tim_16b8c TIM_16B8C: Output compare pulse is inaccurate YES
MUCts04199 pwm_8b8c PWM: Wrong output value after restart from stop or wait mode YES
MUCts04203 pwm_8b8c PWM: Wrong output level after shutdown restart in 16bit concatenated channel mode YES



Tagged breakpoints missed if tag attach and interrupt are simultaneous MUCts01493

Description

The errata concerns the DBG-CPU interface in DBG mode whilst configured

for tagging. If an interrupt occurs at the moment that a tag is attached
to an opcode being loaded into the instruction queue, the flag will get
set, but the part may not enter active BDM mode.

Using the DBG configuration BDM=DBGBRK=1, BEGIN=0, an event causing a
flag to be set should cause a break to BDM. The flag gets set, but the
part does not enter active BDM mode. The CPU executes the interrupt
service routine, instead, and returns to the correct position in the
program flow, but the breakpoint to BDM is missed.

The problem does not occur if the DBG module is configured for operation
in BKP mode (BKABEN=1). This is because, even if the flag bit is set,
the BKABEN bit is not cleared. On returning from the interrupt service
routine, the tag is re-applied when the PC is fetched after the
interrupt service routine, and the part enters BDM after the interrupt
service routine. In BKP mode with TRGSEL=0, no flags are set when a
taghit occurs.

In BKP mode with TRGSEL=1, the flag is also set erroneously on entering
the interrupt service routine. However, it is unlikely that a user would
be affected by the flag being set early (unless the service routine were
exceptionally long), due to the length of time needed to read out the
DBGSR (flag bits) over the BKGD pin; typically, during this time, the
part would enter active BDM when the tag is re-applied.

Workaround


None.



Return from STOP malfunctionMUCts01534

Description

When the MCU returns from STOP mode, the internal VDD level can dip

below the LVR level leading to a Power On Reset (POR) event.


Workaround


1) Do not use STOP mode.








Reduced flash program temperature range and increased programming timeMUCts01654

Description

The flash program temperature range specification has been reduced. The

specification now stipulates that flash program operations must take
place between temperatures of -20C and 125C ambient.

In addition, the flash program times have been increased as follows:

Programming Time
Min. Max.
Single Word Program (Tswpgm) 66.0us 99.2us
Flash Row Program - Consecutive Word (Tbwpgm) 40.4us 57.8us
Flash Row Program - 64 words (Tbrpgm) 2608.7us 3742.7us

Actual programming time will vary between the above bounds depending on
flash clock and bus clock frequencies.

Important Notes:
1) Program time is internally controlled by the flash state machine.
No action needs to be taken by users in connection with this erratum.
2) Both flash erase and flash read temperature specifications and
operation times are unaffected by this erratum.
3) EEPROM is unaffected by this erratum.


Workaround


None.



Flash test read issueMUCts01677

Description

The Flash memory test module read-access timing limits the bus 

frequency achievable for production test.



Workaround


Operate the device at a maximum frequency of 18 MHz.






Possible manipulation of return address when exiting BDM active modeMUCts01861

Description

Upon leaving BDM active mode, the CPU return address is stored

temporarily for a few cycles in the BDM shift register. If a BDM command
transmission is detected during this time, the return address will be
manipulated in the BDM shift register. This situation is likely to occur
when a CPU BGND instruction is executed in user code during debugging
under the following conditions:

(i) The BDM module is not enabled AND
(ii) BDM commands are sent from the host

If this situation occurs, the CPU will execute BDM firmware and will
check the status of the ENBDM bit in the BDMSTS register. If the BDM is
disabled, the ENBDM bit will be clear, and hence the BDM firmware will
be exited and the shift register manipulation described above will occur.

Workaround


Avoid using the BGND instruction when the ENBDM bit in the BDMSTS

register is cleared.



EEPROM Program Failure during Sector-ModifyMUCts02387

Description

At oscillator frequencies above 4MHz the Program step of the EEPROM

Sector-Modify command can fail depending on the bus frequency. As a
result, no programming of the EEPROM occurs. There is no impact to the
Erase step of the Sector-Modify command. Since a partial programming of
the word cannot occur, there is not a reliability issue caused by the
Sector-Modify command if the programmed word is verified.

Oscillator Bus
Frequency Frequency
---------- ----------------------
4MHz No Issue
8MHz Fbus <20MHz : No issue
16MHz Fbus <16MHz : No issue




Workaround


Use seperate Erase and Program commands in place of the Sector-Modify

command. If the Sector-Modify command is used and fails the program step
as confirmed by a user verification step, a Program command alone can be
used to effectively complete the operation since the erase step does
successfully erase the sector.



MEBI: Missing ECLK edge on first external access after mode switchingMUCts02415

Description

If the ECLK is used as an external bus control signal (ESTR=1) the first

external access is lost after switching from a single chip mode with
enabled ECLK output to an expanded mode. The ECLK is erroneously held in
the high phase thus the first external bus access does not generate a
rising ECLK edge for the external logic to latch the address. The ECLK
stretches low after the lost access resulting in all following external
accesses to be valid.

Workaround


Enter expanded mode with ECLK output disabled (NECLK=1). Enable the ECLK

after switching the mode before executing the first external access.



SPI: Disabling slave SPI together with clearing CPHA while SS low locks transmit shift register for the next transmissionMUCts03403

Description

With the SPI configured as a slave, clearing the SPE bit (to disable 

the SPI) together with clearing the CPHA bit while the SS pin is low
causes the transmit shift register to be locked for the next
transmission following the SPI being re-enabled as a slave with SS
still being low.

This means new transmit data is not accepted for the first
transmission after re-enabling the SPI (indicated by SPTEF staying low
after storing transmit data into SPIDR), but for the next following
transmission.



Workaround


When disabling the slave SPI, CPHA should not be cleared at the same time. 




ATD: Abort of an A/D conversion sequence with write to ATDxCTL0/1/2/3 may not workMUCts03468

Description

Starting a conversion with a write to ATDxCTL5 or on an external 

trigger event, and aborting immediately afterwards with a write to
ATDxCTL0, ATDCTL1, ATDxCTL2 or ATDxCTL3 can fail to stop the
conversion process.




Workaround


Only write to ATDxCTL4 to abort an ongoing conversion sequence.


Use the recommended start and abort procedures from the Block Guide.
Section : Initialization/Application Information
Subsection: Setting up and starting an A/D conversion
Subsection: Aborting an A/D conversion






FTS256K2ECC: Blind Spot in Data Compress Command AlgorithmMUCts03543

Description

If the range of Flash addresses to be compressed is 32K or greater, the

data at one of the addresses will be effectively ignored. The address
affected is 32K from the upper address read in the data compress
algorithm, e.g., for an address range of 32K, the first data read in the
algorithm will not affect the final signature provided by the algorithm.


Workaround


Limit range of addresses to be compressed to less than 32K addresses.


Execute multiple data compress commands to compress larger Flash address
ranges.



MSCAN: Corrupt ID may be sent in early-SOF conditionMUCts03569

Description

The initial eight ID bits will be corrupted if a message is set up for

transmission during the third bit of INTERMISSION and a dominant bit is
sampled leading to an early-SOF*.

The CRC is calculated from the resulting bit stream so that the
receiving nodes will still validate the message.

An early-SOF condition may only occur if the oscillators in the network
operate at a tolerance range which could lead to a cumulated phase error
after 11 bit times larger than phase segment 2.

In case arbitration is lost during transmission of the corrupt
identifier, a non-corrupted ID will be sent with the next attempt if the
transmit request remains active.

*The CAN protocol condition referred to as 'early-SOF' in this erratum
is detailed in "Bosch CAN Specification Version 2.0" Part A, section 9,
and a Note to section 3.2.5 INTERFRAME SPACING – INTERMISSION in Part B.

Workaround


Due to increased oscillator tolerance a transmission start in the third


bit of intermission is possible and allowed. The errata can be avoided
when calculating the maximum oscillator tolerance of the overall CAN
system. The phase error after 11 bit times due to the oscillator
tolerance should be smaller than phase segment 2.

If an early-SOF cannot be avoided the following methods will provide
prevention:

- Assigning the same value to all upper eight ID bits in the network
- Allocating dedicated data length codes (DLC) to every identifier used
in the network and checking for correspondence after reception
- Assigning only IDs (x) which do not consist of a combination of other
assigned IDs (y,z) and using the acceptance filters to reject
erroneous messages, i.e.
- for standard frames: IDx[11:0] != {IDy[11:3], IDz[2:0]}
- for extended frames: IDx[28:21] != {IDy[28:21],IDz[20:0]}



ADC: conversion does not start with 2 consecutive writes to ATDCTL5MUCts03685

Description

When the ATD is started with write to ATDCTL5

and, which is very unusual and not necessary,
within a certain period again started with write
to ATDCTL5. The conversion will not start at all.
This does only happen if the two consecutive writes to ATDCTL5 occur
within one "ATD clock period". An ATD clock period is defined by a full
rollover of the ATD clock prescaler. That is for example PRS[4:0] = 2 -
> (2+1)*2 = within 6 bus cycles.


Workaround


Only write once to ATDCTL5 when starting a conversion.


Use the recommended start and abort procedures from the Block Guide.
Section : Initialization/Application Information Subsection: Setting up
and starting an A/D conversion Subsection: Aborting an A/D conversion



PWM: Emergency shutdown input can be overruledMUCts04073

Description

If the PWM emergency shutdown feature is enabled (PWM7ENA=1) and PWM

channel 7 is disabled (PWME7=0) another lower priority function
available on the related pin can take control over the data direction.
This does not lead to a problem if input mode is maintained. If the
alternative function switches to output mode the shutdown function may
unintentionally be triggered by the output data.


Workaround


When using the PWM emergency shutdown feature the GPIO function on the

pin associated with PWM channel 7 should be selected as an input.

In the case that this pin is selected as an output or where an
alternative function is enabled which could drive it as an output,
enable PWM channel 7 by setting the PWME7 bit. This prevents an
active shutdown level driven on the (output) pin from resulting in an
emergency shutdown of the enabled PWM channels.




TIM:Normal Output Compare event happens on setting OC7M bit if OM/OL=0 MUCts04159

Description

When an OC7M bit is set, an erroneous normal output compare event can 

happen on a timer port if the compare action is selected as "Timer
disconnected from output pin logic ".

Corresponding configuration:
* TIOSx = 1 --> Output compare mode
* OMx = OLx = 0 --> Output compare logic disconnected from the pin
* OC7Mx = 1 --> Mask bit set for OC7 event







Workaround


Set OC7Mx = 1 only for channels where the output compare action should 

drive the pin, and OC7Mx = 0 for all other channels where the pin is
required to be disconnected from the output compare logic.



TIM_16B8C: Output compare pulse is inaccurateMUCts04161

Description

The pulse width of an output compare (which resets the free running

counter when TCRE = 1) will measure one more bus clock cycle than
expected.



Workaround


The specification has been updated. Please refer to revision 01.09 (07


May 2010) or later.

In description of bitfield TCRE in register TSCR2,a note has been added:
TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler
counter width" + "1 Bus Clock". When TCRE is set and TC7 is not equal to
0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it
will last only one bus cycle then reset to 0.









PWM: Wrong output value after restart from stop or wait modeMUCts04199

Description

In low power modes (stop/p-stop/wait – PSWAI=1) and during PWM PP7

de-assert and when PWM counter reaching 0, the PWM channel outputs
(PP0-PP6) cannot keep the state which is set by PWMLVL bit.



Workaround


Before entering low power modes, user can disable the related PWM 

channels and set the corresponding general-purpose IO to be the PWM
LVL value. After a intend period, restart the PWM channels.




PWM: Wrong output level after shutdown restart in 16bit concatenated channel modeMUCts04203

Description

When the PWM is used in 16-bit (concatenation) channel and the emergency

shutdown feature is being used, after de-asserting PWM channel 7
(note:PWMRSTRT should be set) the PWM channels (PP0-PP6) do not show the
state which is set by PWMLVL bit when the 16-bit counter is non-zero.


Workaround


If emergency shutdown mode is required:



In 16-bit concatenation mode, user can disable the related PWM
channels and set the corresponding general-purpose IO to be the PWM
LVL value. After a intend period, restart the PWM channels.




© NXP Semiconductors, Inc., 2011. All rights reserved.