QorIQ P4080 Communications Processor
The QorIQ P4080 processor, the first product offered in the QorIQ P4 platform series, delivers industry leading performance in the under 30-watt power category. It combines eight Power Architecture™ e500mc cores – operating at frequencies up to 1.5 GHz – with high-performance datapath acceleration logic, and network and peripheral bus interfaces. All this designed for 45nm technology to deliver high-performance, next-generation networking services in a very low power envelope.
The QorIQ P4080 processor can be used for combined control, datapath, and application layer processing. Its high level of integration offers significant performance benefits compared to multiple discrete devices, while also greatly simplifying board design. The processor is well-suited for applications that are highly compute-intensive, I/O intensive, or both, making it ideal for applications such as enterprise and service provider routers, switches, base-station controllers radio network controllers (RNCs), longterm evolution (LTE) and general-purpose embedded computing systems in the networking, telecom/datacom, wireless infrastructure, military and aerospace markets.
Features
- Eight high-performance Power Architecture e500mc cores, each with a 32 KB Instruction and Data L1 Cache and a private 128 KB L2 Cache:
- 3 levels of instructions - user, supervisor, and hypervisor
- Independent boot and reset
- Secure boot capability
- 2 MB shared L3 CoreNet platform cache
- Hierarchical interconnect fabric:
- CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points
- 800 Gbps coherent read bandwidth
- Queue Manager fabric supporting packet-level queue management and quality of service scheduling
- Two 64-bit DDR2/DDR3 SDRAM memory controllers with ECC and interleaving support
- Datapath Acceleration Architecture incorporating acceleration for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion management
- Hardware Buffer Management for buffer allocation and de-allocation
- Encryption (SEC 4.0)
- RegEx Pattern Matching (PME 2.0)
- Ethernet interfaces:
- Two 10 GBps Ethernet (XAUI) controllers
- Eight 1 GBps Ethernet (SGMII) controllers
- High-speed peripheral interfaces:
- Three PCI Express v2.0 controllers/ports running at up to 5GHz
- Two Serial RapidIO® 1.2 controllers/ports running at up to 3.125 GHz
- Additional peripheral interfaces:
- Two USB controllers with ULPI interface to external PHY
- SD/MMC
- SPI controller
- Four I2C controllers
- Two dual UARTs (DUART)
- Enhanced local bus controller (eLBC)
- Multicore programmable interrupt controller (PIC)
- Two 4-channel DMA engines
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