The QorIQ™ P1022 family of processors is designed to deliver complex application processing performance with exceptional feature integration and high-speed connectivity for IP networking and advanced media processing applications. It combines dual e500 processor cores, built on Power Architecture® technology, with enhanced system peripherals and interconnect technology to balance processor performance with I/O system throughput. The P1022 processor includes advanced power and energy management features that enable developers to design next-generation embedded Internet media processing applications with energy efficiency levels under the environmental and governmental energy regulatory requirements. The P1013 is a single core version of the P1022 family.
Advanced Energy-Efficient Modes
Balancing the performance requirements for powerful new networking- and Internet-centric applications, with the increasing concerns over energy consumption, is driving manufacturers to develop intelligent strategies for optimizing performance within specific energy budgets. This is a key challenge for the next generation green embedded systems. The P1022 processor implements sophisticated power-saving modes for managing energy consumption in both dynamic and static power modes. These include the traditional nap, doze and plus jog (dynamic frequency scaling) and packet-lossless deep sleep modes. Designers will be able to leverage these modes to efficiently match work accomplished with the correct level of energy consumed.
Applications
The combination of these features makes the P1022 processor an optimal embedded processing solution for Ethernet or PCI Express interworking applications, such as enterprise networking, industrial, storage, security and office automation applications. Examples include control plane processing, protocol processing, media processing and while producing an engaging human machine interface.
Features
- Dual (P1022) or single (P1013) high-performance Power Architecture e500v2 cores
- 36-bit physical addressing
- Double-precision floating-point support
- Signal-processing engine (SPE) APU (auxiliary processing unit)
- 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache for each core
- 400 MHz to 1055 MHz core clock frequency
- 256-Kbyte L2 cache with ECC, also configurable as SRAM and stashing memory
- 64-bit DDR2/DDR3 SDRAM memory controller with ECC support
- Two 10/100/1000 Mbps virtualized enhanced three-speed Ethernet controllers (eTSECs)
- TCP/IP acceleration and classification capabilities
- IEEE® 1588 support
- Loseless flow control
- RMII, RGMII, SGMII
- Integrated security engine (optional)
- Crypto algorithm support includes 3DES, AES, RSA/ECC, MD5/SHA, ARC4, Kasumi, Snow 3G and FIPS deterministic RNG
- Single pass encryption/message authentication for common security protocols (IPsec, SSL, SRTP, WiMAX)
- XOR acceleration
- High-speed interfaces (not all available simultaneously)
- Six SerDes lanes (multiplexed across controllers)
- One x4 and two x1 PCI Express interfaces
- Two serial ATA (SATA) interfaces
- Two SGMII interfaces
- Audio Visual Interfaces
- LCD interface supporting a display of 1280x1024P @ 60 Hz, 24 bits per pixel
- I2S interface with maximum sampling frequency of 192 KHz
- VoIP TDM Interface
- support for upto 128 channels
- Two high-speed USB controllers (USB 2.0)
- Host and device support
- Enhanced host controller interface (EHCI)
- ULPI interface to PHY
- Enhanced secure digital host controller (SD/MMC)
- Serial peripheral interface
- Integrated security engine (SEC) with XOR acceleration
- Programmable interrupt controller (PIC) compliant with Open-PIC standard
- Dual four-channel DMA controllers
- Dual I2C controllers, DUART, timers
- Enhanced local bus controller (eLBC)
- Advanced Power and Energy Management
- Up to 87 general-purpose signals
- Package: 689-pin temperature-enhanced plastic BGA (TEPBGA2)
Target Applications
- Enterprise networking
- Industrial
- Storage
- Security
- Office automation applications
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