The MSC8126 is a highly integrated system-on-a-chip that combines four StarCore SC140 extended cores with an RS-232 serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a flexible system interface unit (SIU), an Ethernet interface, a Turbo Coprocessor (TCOP), a Viterbi Coprocessor (VCOP), and a multi-channel DMA controller. The four extended cores can deliver up to 8000 DSP MMACS performance at up to 500 MHz.
Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers. The MSC8126 targets high-bandwidth highly computational DSP applications and is optimized for wireless transcoding and packet telephony as well as high-bandwidth base station applications. The MSC8126 delivers enhanced performance while maintaining low power dissipation and greatly reduces system cost.
The MSC8126 device is designed to provide an optimal solution for 3G wireless base stations, to help eliminate many of the costly and power hungry ASICs and FPGAs required in today's systems for both symbol rate and for chip rate assist. In addition, the MSC8126 device allows customers to add next-generation features that efficiently use available frequencies and higher bit rates in 3G systems.
Efficient application software development is key in Freescale's strategy to expedite customers' time to market. Developers can take advantage of development tools and real-time operating systems (RTOS) from Freescale and third-party suppliers. In addition Freescale is partnering with third-party vendors to provide integrated systems solutions that include GSM, CDMA, TDMA, and ITU G.7xx speech coders, hybrid echo cancellation, fax, modem, and xDSL software.
View Block DiagramFeatures
Four 400/500 MHz StarCore SC140 DSP extended cores
- 16 ALUs on a chip deliver up to 6400/8000 MMACS
- Performance equivalent to a 1.6/2.0 GHz SC140 Core
- Industry's largest on-chip SRAM memory
- 1436 KB of internal SRAM
- Efficient multi-level memory hierarchy
- External bus configurable as:
- 32-bit data system bus/64-bit direct slave interface (DSI).
- 64-bit data system bus/32-bit DSI.
- Ethernet (MII/RMII)/32-bit system bus/32-bit DSI.
- Four independent Time-Division Multiplex (TDM) Interfaces
- 256 channels total for connectivity to T1/E1, MVIP, and H.110 interfaces
- Up to 62.5 Mbps per TDM interface
- Flexible memory controller accesses various external memories, including SDRAMs, SRAMs, SSRAMs, EPROMs, and Flash
- Internal DMA controller that supports 16 time-multiplexed unidirectional channels, enabling data transfers of to and from the SC140 core M1 memory, the M2 memory, and the serial interfaces
- Ethernet interface designed to comply with IEEE® Std 802.3TM, 802.3uTM, 802.3xTM, and 802.3acTM:
- Gives direct access to internal memories via the DMA controller
- Supports the 10/100 Mbps and 10 Mbps media-independent interfaces (MIIs), 10/100 Mbps reduced media-independent interface (RMII), and 10/100 Mbps serial media-independent interface (SMII)
- Two internal coprocesssors (TCOP and VCOP) to provide special-purpose processing capability in parallel with the core processors
- At 500 MHz, TCOP supports twenty turbo-coding 384 kbps channels.
- At 500 MHz, VCOP supports 400 3GPP 12.2 kbps AMR channels and 200 blind transport format detection (BTFD) channels
The MSC8126 device is manufactured in 90 nm process technology. The device uses a 20 mm x 20 mm Flip Chip Ball-Grid Array (FC-BGA) package, available with lead-free or lead-bearing spheres.
Availability
Contact your local Sales office for information about availability.
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