Features

Superscalar Microprocessor

The MPC750/740 microprocessors are superscalar, capable of issuing three instructions per clock cycle into six independent execution units:

• Two integer units
• Load/Store unit
• Floating-point unit
• System register unit
• Branch processing unit

The ability to execute multiple instructions in parallel, to pipeline instructions, and the use of simple instructions with rapid execution times yields maximum efficiency and throughput for MPC750/740 systems.

Power Management

The MPC750/740 microprocessors feature a low-power 2.6-volt or 1.9-volt design with three power-saving modes-doze, nap and sleep. These user-programmable modes progressively reduce the power drawn by the processor. These low-power microprocessors offer dynamic power management to selectively activate functional units as they are needed by the executing instructions. Both microprocessors also provide a thermal assist unit and instruction cache throttling for software-controllable thermal management.

Cache and MMU Support

The MPC750/740 microprocessors have separate 32-Kbyte, physically-addressed instruction and data caches. Both caches are eight-way set-associative. The additional dedicated L2 cache interface with on-chip L2 tags is provided only by the MPC750 microprocessor. MPC750/740 microprocessors contain separate memory management units (MMUs) for instructions and data, supporting 4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of physical memory. Access privileges and memory protection are controlled on block or page granularities. Large, 128-entry translation lookaside buffers (TLBs) provide efficient physical address translation and support for demand virtual-memory management on both page- and variable-sized blocks.

Flexible Bus Interface

MPC750/740 microprocessors have a 64-bit data bus and a 32-bit address bus. Support is included for burst, split and pipelined transactions. The interface provides snooping for data cache coherency. Both microprocessors maintain MEI coherency protocol in hardware, allowing access to system memory for additional caching bus masters, such as DMA devices.