The MPC561 is a high-speed 32-bit control unit that combines high-performance data manipulation capabilities and with powerful peripheral subsystems. This MCU is built up from standard modules that interface through a common intermodule bus (IMB).
View Block DiagramFeatures
Precise exception model
- Floating point
- Extensive system development support
- On-chip watchpoints and breakpoints
- Background debug mode (BDM)
- IEEE-ISTO 5001-1999 NEXUS Class 3 Debug Interface
- True 5-V I/O
- Two time processing units (TPU3) with eight Kbytes DPTRAM
- 22-channel MIOS timer (MIOS14)
- Two queued analog-to-digital converter modules (QADC64_A, QADC64_B) providing a total of 32 analog channels
- Three TouCAN modules (TOUCAN_A, TOUCAN_B, TOUCAN_C)
- One queued serial module with one queued SPI and two SCIs (QSMCM) 32-Kbyte static RAM (CALRAM)
Product Specifications
| Bus Frequency - Max (MHz) | 56, 40 |
| Serial Interface - Type | QSPI, SCI, CAN, SPI, SCI, CAN |
| A/D Converter - Channels | 32 |
| Timers - Channels | 54 |
| I/O Pins | 56 |
