Features

Freescale's e200z6 Core

• High-performance 132 MHz 32-bit core built on Power Architecture technology with Variable Length Encoding (VLE)
• Memory management unit (MMU) with 32-entry fully associative translation lookaside buffer (TLB)
• SPE (signal processing extension): DSP, SIMD and floating point capabilities

Memory

• 2 MB of embedded Flash memory with Error Correction Coding (ECC) and Read While Write capability (RWW)
• 64 KB on-chip static RAM with Error Correction Coding (ECC)
• 8 KB of cache (with line-locking) that can be configured as additional RAM

System

• An enhanced time processor unit (eTPUs) with 32 I/O channels and 14.5k of designated SRAM
• 32-channel eDMA (Enhanced Direct Memory Access) controller
• Interrupt controller (INTC) capable of handling 210 selectable-priority interrupt sources
• Frequency modulated phase-locked loop (FMPLL) to assist in electromagnetic interference (EMI) management
• MPC500 compatible External Bus Interface
• Nexus IEEE-ISTO 5001™ Class 3+ multicore debug capabilities > 5/3.3V IO, 5V ADC, 3.3V/1.8V bus,
• 1.5V core
• 416 pin PBGA and 324 pin PBGA package options
• Temperature Range: -40 to 125ºC

I/O

• 40 channel dual Enhanced queued analog-to-digital converter (eQADC) - up to 12 bit resolution and up to 1.25us conversions, 6 queues with triggering and DMA support
• Three deserial serial peripheral interface (DSPI) modules - 16 bits wide up to 6 chip selects each
• Five controller area network (CAN) modules with 64 buffers each
• Two enhanced serial communication interface (eSCI) modules
• 24 channel enhanced multiple I/O system (EMIOS) with unified channels
• Dual-Channel FlexRay interface
• Fast Ethernet Controller (FEC)

A comprehensive suite of hardware and software development tools are available to help simplify and speed system design. Development support is available from leading tools vendors providing compilers, debuggers and simulation development environments.