The DSP56371 is capable of running delay management, bass management and DTS96/24 while using less than half of the DSP's computing capability. This enables designers to add system enhancements that the discerning audio consumer now expects. The performance increase is made possible through the use of a higher core frequency, fewer memory wait states, a larger amount of on-chip static random access memory (SRAM) and the addition of an Enhanced Filter Coprocessor (EFCOP). By removing the need for external high-speed SRAM and making smaller, less complex boards, the DSP56371 is performance-rich and cost-effective.
Features
Multimode, multichannel decoder software functionality
Dolby and/or DTS license required
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Prologic II
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DTS Neo6
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DTS 2.3
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WMA
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AAC
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Dolby Headphone (DH)
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Dolby Virtual Speaker (DVS)
Digital audio post-processing capabilities
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Parametric EQ
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Tone Control or Graphic EQ
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Dynamic range compression
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Loudness
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Bass Boost
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Speaker Comp
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Fade/Balance
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Music Search
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Compression
Digital Signal Processing Core
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1.25 V core with a 3.3 V peripheral I/O
- Object Code Compatible with the DSP56000 core with highly parallel instruction set
- Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support
- Program Control with position independent code support and instruction cache support
- Six-channel DMA controller
- PLL based clocking with a wide range of frequency multiplications (1 to 255), predivider factors (1 to 3) and power saving clock divider (2I: i=0 to 7). Reduces clock noise
- Internal address tracing support and OnCETM for Hardware/Software debugging
- JTAG port
- Very low-power CMOS design, fully static design with operating frequencies down to DC
- STOP and WAIT low-power standby modes
- EFCOP running concurrently with core
On-chip Memory Configuration
- 16K - 48Kx24 Bit Y-Data RAM and 32Kx24 Bit Y-Data ROM
- 36Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM
- 28K - 64Kx24 Bit Program and bootstrap ROM
- 4Kx24 Bit Program RAM
- Various memory switches available
Peripheral modules
- Enhanced Serial Audio Interface (ESAI_0): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols.
- Enhanced Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony AC97, network and other programmable protocols.
- Serial Host Interface (SHI): SPI and I2C protocols, 10-word receive FIFO, support for 8, 16 and 24-bit words.
- Triple Timer module
- Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958, CP-340 and AES/EBU digital audio formats
- Pins of unused peripherals (except SHI) may be programmed as GPIO lines
Product Specifications
| Core - Type | DSP56300, DSP56300 |
| Core - Number of Cores - Spec | 1, 1 |
| Core - Operating Frequency - Max (MHz) | 150, 180 |
| Co Processor Type | EFCOP |
| Serial Interface - Type | SAI, SHI |
| External Bus Width (bit) | 24 |
| Timers - Channels | 2 |
