The experience of our lab staff and product analysts along with industry-standard techniques and internal tools help us find sub-micron defects among hundreds of millions of transistors on a silicon IC. This is vital to understanding a failure’s root cause, rapid corrective action and preventing similar defects moving forward.
Step 1 - Reproduce the Failure in a Lab Environment
Our product analysts use evaluation boards, digital testers and other tools for this step. Special care (e.g. ESD protection) is taken to make sure new defects are not introduced during this process.
Step 2 - Package Analysis
Using package analysis tools and techniques (e.g. optical inspection, scanning acoustic microscopy, X-ray) we first determine whether or not there is a physical defect with the IC package that surrounds the die.
If the defect is found in the package, we will probe between the package layers to pinpoint the component causing the observed failure mode. It is an iterative process. We start by probing the top 2 package layers. If a defective signal is not detected, the top layer is removed and the next 2 layers are probed.
Step 3 - Defect Spatial Localization
If there is no defect in the package, we remove the device package to expose the silicon die. Localization techniques are used to narrow down the subset of transistors that may have the defect. The key is to inspect the silicon die without destroying it.
Equipment that can detect visible and infrared lights and specially developed software may be used in addition to techniques like light emission microscopy, thermal detection techniques, and diagnostic fault simulation.
Step 4 - Electrical Analysis
Once the problem area has been found, advanced analysis techniques are used to pinpoint the individual transistor or component that may be causing the observed failure mode.
We start with non-destructive techniques (e.g. microprobing) to reduce the number of potentially defective components further. Then destructive techniques (e.g. atomic force probing) might be used find the single component causing the observed failure mode and to characterize the defective component electrically.
If the defective area has been isolated to the device package, then a package analyst probes between the package layers to further
pinpoint the component that is causing the observed failure mode. The analyst starts by probing the top two package layers. If a
defective signal is not detected, then the analyst removes the top layer that was just probed and proceeds to probe the next two package
layers. This iterative process is performed until a defective signal is found.
Step 5 - Physical Analysis
In this step we identify the physical defect that correlates, without question, to the electrical signature of the failing component.
A common technique used is to selectively remove each package layer of the IC or package layer and look at it under an electron or optical microscope. Cross-sectioning may also be used if the defect is between 2 layers. When the defect’s physical and spatial characteristics are not enough, a material analysis may be done. Energy Dispersive Spectroscopy (EDS) and Transmission Electron Microscopy (TEM) are a couple techniques available for use in our product analysis labs.
Step 6 - Documenting the Analysis
The results from the electrical and the physical analysis are used to find the coherent failure mechanism that explains the observed failure mode. We then document the failure root cause and product analysis steps completed. The report is made widely available to the necessary teams so corrective actions can be taken right away.
Next-Generation of Products
Our product analysis labs also work closely with our R&D teams to create the next generation of products that meet your needs and exceed your quality expectations. By finding potential problems early in the product development phase, these labs help us get new products to you faster and at a higher quality.