Freescale has developed a revolutionary new networking system architecture for QorIQ platforms. Next-generation QorIQ LS series processors are built on our new software-aware, core-agnostic Layerscape architecture which delivers unprecedented efficiency and scale for the smarter, more capable networks of tomorrow—end to end.
Layerscape architecture enables next-generation networks with up to 100 Gb/s performance and enhanced packet processing capabilities.
Design effort is simplified with a standard, open programming model and a software-aware architecture framework that enables customers to fully exploit the underlying hardware for maximum optimization, with the capability to easily adapt to network changes for real-time "soft" control over the network.
A uniform hardware and software model provides the compatibility and scalability required for customers designing end-to-end networking equipment from home-to carrier-class products. The unique, core-agnostic architecture incorporates the optimum core for the given application—ARM cores or Power Architecture cores.
Layerscape architecture offers accelerated packet processing with a comprehensive enablement model focused on ease of programmability. Layerscape architecture is comprised of three layers: the general-purpose processing layer (GPPL), the accelerated packet processing layer (APPL) and the express packet I/O layer (EPIL).
The GPPL is composed of highly efficient general-purpose processing nodes, a coherent interconnect and a latency-and bandwidth-tuned memory subsystem. The GPPL enables intelligent routing of inter-CPU traffic and supports application-aware cache warming.
The APPL performs autonomous packet processing or provides offload packet processing functions for the GPPL. It is also flexible enough to enable customers to program value added capabilities in a traditional sequential, synchronous, run to completion model hiding the hardware microarchitecture through embedded C-based structured programming. The APPL consists of:
- Accelerated packet processor
- Decompression engine
- Security engine (SEC)
- Load balancing engine
- Pattern matching engine
- L2-L7 switching
- Packet buffer
The EPIL facilitates true, deterministic wirerate performance between all network interfaces (up to 100G), supporting L2+ switching capabilities. This layer supports I/O protocol specific capabilities including PCI Express®, Ethernet and Interlaken. The EPIL consists of:
- Configurable packet I/O interface which includes parse, classify and distribute