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SBC_driver.h

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00001 /*******************************************************************************/
00013 /*******************************************************************************/
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00046 /*******************************************************************************/
00047 
00048 #ifndef _SBC_DRIVER_H
00049 #define _SBC_DRIVER_H
00050 
00052 #include "typedefs.h" 
00053 
00054 /* Default values for SBC Configuration: */
00055 
00056 #define SBC_TIM1_INIT   SBC_WDOG_350MS
00057 #define SBC_RCR_INIT    0
00058 #define SBC_CAN_INIT    SBC_SLEWRATE0
00059 #define SBC_IOR_INIT    0
00060 #define SBC_WUR_INIT    SBC_L0L1HIGH|SBC_L2L3BOTH
00061 #define SBC_TIM2_INIT   SBC_CYCLICSENSE_388MS
00062 #define SBC_LPC_INIT    0
00063 #define SBC_INTR_INIT   SBC_CANF|SBC_VDDTEMP|SBC_INTVSUPLOW
00064 
00065 /* Read/ Write bit */
00066 #define SBC_R           0b00000000
00067 #define SBC_W           0b00010000
00068 
00069 /* SBC Register adresses */
00070 #define SBC_MCR         0b00000000
00071 #define SBC_RCR         0b00100000
00072 #define SBC_CAN         0b01000000
00073 #define SBC_IOR         0b01100000
00074 #define SBC_WUR         0b10000000
00075 #define SBC_TIM         0b10100000
00076 #define SBC_LPC         0b11000000
00077 #define SBC_INTR        0b11100000
00078 
00079 
00080 /* MCR, Mode Control register */
00081         /* Write */
00082 #define SBC_MCTR2       0b00000100
00083 #define SBC_MCTR1       0b00000010
00084 #define SBC_MCTR0       0b00000001
00085         /* Read  */
00086 #define SBC_BATFAIL     0b00001000
00087 #define SBC_VDDPRE      0b00000100
00088 #define SBC_GFAIL       0b00000010
00089 #define SBC_WDRST       0b00000001
00090         /* MCR Control Bits */
00091 #define SBC_DEBUGMODE   0x00
00092 #define SBC_NORMAL      SBC_MCTR0
00093 #define SBC_STANDBY     SBC_MCTR1
00094 #define SBC_STOP        SBC_MCTR1|SBC_MCTR0
00095 #define SBC_SLEEP       SBC_MCTR2
00096 #define SBC_DBGNORMAL   SBC_MCTR2|SBC_MCTR0
00097 #define SBC_DBGSTANDBY  SBC_MCTR2|SBC_MCTR1
00098 #define SBC_DBGSTOP     SBC_MCTR2|SBC_MCTR1|SBC_MCTR0
00099 
00100 
00101   /* RCR, Reset Control Register */    
00102 #define SBC_WDSTOP      0b00001000
00103 #define SBC_NOSTOP      0b00000100
00104 #define SBC_CANSLEEP    0b00000010
00105 #define SBC_RSTTH       0b00000001
00106 
00107 
00108 /* CAN Register */
00109 /* Write */
00110 #define CANCLR          0b00001000
00111 #define SBC_SC1         0b00000100
00112 #define SBC_SC0         0b00000010
00113 #define SBC_MODE        0b00000001
00114         /* Read */
00115 #define SBC_CANWU       0b00001000
00116 #define SBC_CAN_F       0b00000100
00117 #define SBC_CAN_UF      0b00000010
00118 #define SBC_THERM_CUR   0b00000001
00119 /* High Speed Can Transceiver Modes */
00120 #define SBC_SLEWRATE0           0x00
00121 #define SBC_SLEWRATE1           SBC_SC0
00122 #define SBC_SLEWRATE2           SBC_SC1
00123 #define SBC_SLEWRATE3           SBC_SC1|SBC_SC0
00124 #define SBC_SLEEP_WKPDISABLE    SBC_MODE|SBC_SC0  
00125 #define SBC_SLEEP_WKPENABLE     SBC_MODE
00126 
00127 
00128 /* IOR, Input/Output Register */
00129 /* Write */
00130 #define SBC_HSON        0b00000100
00131         /* Read */
00132 #define SBC_V2LOW       0b00001000
00133 #define SBC_HSOT        0b00000100
00134 #define SBC_VSUPLOW     0b00000010
00135 #define SBC_DEBUG       0b00000001
00136 
00137 
00138 /* WUR, Wake Up Register */
00139 /* Write */
00140 #define SBC_LCTR3       0b00001000
00141 #define SBC_LCTR2       0b00000100
00142 #define SBC_LCTR1       0b00000010
00143 #define SBC_LCTR0       0b00000001
00144 /* Read */
00145 #define SBC_L3WU        0b00001000
00146 #define SBC_L2WU        0b00000100
00147 #define SBC_L1WU        0b00000010
00148 #define SBC_L0WU        0b00000001
00149 /* Control Bits */
00150 #define SBC_L0L1DISABLED    0x00
00151 #define SBC_L0L1HIGH        SBC_LCTR0
00152 #define SBC_L0L1LOW         SBC_LCTR1
00153 #define SBC_L0L1BOTH        SBC_LCTR1|SBC_LCTR0
00154 #define SBC_L2L3DISABLED    0x00
00155 #define SBC_L2L3HIGH        SBC_LCTR2
00156 #define SBC_L2L3LOW         SBC_LCTR3
00157 #define SBC_L2L3BOTH        SBC_LCTR3|SBC_LCTR2
00158 
00159 
00160 /* TIM1/2, Timing Registers */
00161 #define SBC_TIM1        0b00000000
00162 #define SBC_TIM2        0b00001000
00163 /* TIM1 Write */
00164 #define SBC_WDW         0b00000100
00165 #define SBC_WDT1        0b00000010
00166 #define SBC_WDT0        0b00000001
00167 /* TIM2 Write */
00168 #define SBC_CSP2        0b00000100
00169 #define SBC_CSP1        0b00000010
00170 #define SBC_CSP0        0b00000001
00171 /* TIM1/TIM2 Read */
00172 #define SBC_CANL2VDD    0b00001000
00173 #define SBC_CANL2BAT    0b00000100
00174 #define SBC_CANL2GND    0b00000010
00175 #define SBC_TXPD        0b00000001
00176 /* Watchdog Periods */
00177 #define SBC_WDOG_10MS           0x00
00178 #define SBC_WDOG_45MS           SBC_WDT0
00179 #define SBC_WDOG_100MS          SBC_WDT1
00180 #define SBC_WDOG_350MS          SBC_WDT1|SBC_WDT0
00181 #define SBC_WDOG_WDW_10MS       SBC_WDW
00182 #define SBC_WDOG_WDW_45MS       SBC_WDW|SBC_WDT0
00183 #define SBC_WDOG_WDW_100MS      SBC_WDW|SBC_WDT1
00184 #define SBC_WDOG_WDW_350MS      SBC_WDW|SBC_WDT1|SBC_WDT0
00185 /* Cyclic Sense Timings */
00186 #define SBC_CYCLICSENSE_5MS     0x00
00187 #define SBC_CYCLICSENSE_9MS     SBC_CSP0
00188 #define SBC_CYCLICSENSE_18MS    SBC_CSP1
00189 #define SBC_CYCLICSENSE_37MS    SBC_CSP1|SBC_CSP0
00190 #define SBC_CYCLICSENSE_74MS    SBC_CSP2
00191 #define SBC_CYCLICSENSE_95MS    SBC_CSP2|SBC_CSP0
00192 #define SBC_CYCLICSENSE_191MS   SBC_CSP2|SBC_CSP1
00193 #define SBC_CYCLICSENSE_388MS   SBC_CSP2|SBC_CSP1|SBC_CSP0
00194 
00195 
00196 /* LPC, Low Power Control Register */
00197 /* Write */
00198 #define SBC_LX2HS       0b00001000
00199 #define SBC_FWU         0b00000100
00200 #define SBC_CAN_INT     0b00000010
00201 #define SBC_HSAUTO          0b00000001
00202 /* Read */
00203 #define SBC_CANH2VDD    0b00001000
00204 #define SBC_CANH2BAT    0b00000100
00205 #define SBC_CANH2GND    0b00000010
00206 #define SBC_RXPR        0b00000001
00207 
00208 
00209 /* INTR, Interrupt Register */
00210 /* Write */
00211 #define SBC_INTVSUPLOW  0b00001000
00212 #define SBC_HSOT_V2LOW  0b00000100
00213 #define SBC_VDDTEMP     0b00000010
00214 #define SBC_CANF        0b00000001
00215 /* Read */
00216 #define SBC_HSOT        0b00000100
00217 
00218 
00219 
00223 void vfnSBC_Write (UINT8 u8TXByte);
00224 
00226 UINT8 u8SBC_Read (UINT8 u8TXByte);
00227 
00229 UINT8 u8SBC_StandbyMode (void);
00230 
00232 void vfnSBC_DebugMode (void);
00233 
00235 void vfnSBC_ClearWatchdog(void);
00236 
00237 
00238 #endif /* _SBC_DRIVER_H */
00239 
00240 /*******************************************************************************/